STS3-1800P

Calibration artifact: 18nm step height, 3/10/20µm pitch, NIST traceable. These VLSI surface topography standards have a variety of Step Heights and Pitches. They incorporate features defined in all three directions for SPM calibration. The STS3 Models are pattered in a layer of SiO₂ and include a 10µm VLSI reference die. These standards are certified by VLSI and traceable to NIST for pitch and step height and meet MIL-STD-45662A. All die are 8mm x 8mm and unmounted .View...

Calibration artifact: 44nm step height, 3/10/20µm pitch, NIST traceable. These VLSI surface topography standards have a variety of Step Heights and Pitches. They incorporate features defined in all three directions for SPM calibration. The STS3 Models are pattered in a layer of SiO₂ and include a 10µm VLSI reference die. These standards are certified by VLSI and traceable to NIST for pitch and step height and meet MIL-STD-45662A. All die are 8mm x 8mm and unmounted .View...

Calibration artifact: 100nm step height, 3/10/20µm pitch, NIST traceable. These VLSI surface topography standards have a variety of Step Heights and Pitches. They incorporate features defined in all three directions for SPM calibration. The STS3 Models are pattered in a layer of SiO₂ and include a 10µm VLSI reference die. These standards are certified by VLSI and traceable to NIST for pitch and step height and meet MIL-STD-45662A. All die are 8mm x 8mm and unmounted .View...