STR3-180P

Calibration artifact: 44nm step height, 3µm pitch. This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance. The silicon die with patterned layer of SiO₂ is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or traceable to NIST.View...

Calibration artifact: 100nm step height, 3µm pitch. This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance. The silicon die with patterned layer of SiO₂ is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or traceable to NIST.View...

Calibration artifact: 180nm step height, 3µm pitch. This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance. The silicon die with patterned layer of SiO₂ is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or traceable to NIST.View...